1. Field of the Invention
The present invention relates to frequency synthesizers. More particularly, the present invention relates to synthesizers configured to provide a high frequency output, such as from 600-1200 MHz, while supporting a high output resolution, such as 0.1 Hz, and a low settling time, such as 72 xcexcsec or less.
2. Description of the Related Art
FIG. 1 shows traditional components for a xe2x80x9cfixed Rxe2x80x9d frequency synthesizer used as a component in a synthesizer operating from 600-1200 MHz and providing a 0.1 Hz resolution with a 72 xcexcsec settling time. As shown, the fixed R frequency synthesizer of FIG. 1 includes a reference oscillator 100 providing a signal having a frequency FR. A frequency divider 102 divides the output from reference oscillator 100 by a fixed amount R to provide a first input to a phase detector 104. A voltage controlled oscillator (VCO) 106 provides the synthesizer output having a frequency Fo. A frequency divider 108 divides the frequency Fo of the VCO 106 by N to provide a second input to phase detector 104. The output of the phase detector 104 is provided through an integrator 110 to the voltage control input of VCO 106.
In operation, the value for R remains fixed, while N is incrementally changed to control the frequency Fo. The frequency (Fp) of signals provided at inputs of phase detector 104 remain constant. Thus, Fp=FR/R=Fo/N, and Fo is obtained as Fo=FRN/R. Resolution (RES) is then obtained by taking the difference in frequencies of the output signal Fo as N in frequency divider 108 is incrementally changed or RES=FR(N+1)/Rxe2x88x92FRN/R=FR/R. Settling time (tsettle) is determined in terms of the frequency Fp of signals provided to phase detector 104 as follows: tsettle=4.5/(2xcfx80(Fp/10)).
Table A shows values for Fo, N and R in the circuit of FIG. 1 with FR=10 MHz, a resolution of 1 KHz and a desired Fo=10.245 MHzxc2x110 KHz. Note with RES=FR/R, R is 10,000. Further, Fp=FR/R=1 KHz making tsettle=4.5/(2xcfx80(Fp/10))=7.2 msec.
Utilizing the circuit of FIG. 1 with a higher frequency output signal Fo, such as 600 MHz, to obtain a high resolution the settling time will be very large. For instance, if a desired RES=Fp=1 Hz, settling time tsettle will be 7 seconds.
To obtain a smaller settling time while maintaining a high resolution, a plurality of the fixed R synthesizers as shown in FIG. 1 can be combined to form a xe2x80x9cdivide sumxe2x80x9d synthesizer as shown in FIGS. 2A and 2B. FIG. 2A shows a fine resolution portion of a divide sum synthesizer, while FIG. 2B shows a coarse resolution portion of the divide sum synthesizer. The divide sum synthesizer of FIGS. 2A-2B can support a 600-1200 MHz output while providing a 0.1 Hz resolution and 72 xcexcsec settling time.
The fine resolution portion of the divide sum synthesizer shown in FIG. 2A includes fixed R synthesizers 201-203. The fixed R synthesizers 201-203 utilize a common reference oscillator 205 providing a signal having a frequency FR. The common reference oscillator 205, such as a 10 MHz source shown, can be provided from a standard external signal source enabling the output of the divide sum synthesizer to be synchronized, or coherent with the common reference output FR.
The output of the fixed R synthesizer 201 (F2) is provided to a first input of a mixer 206, while a second input of the mixer 206 is provided from an output (F1) of a VCO 208. The output of VCO 208 is further provided through a frequency divider 210 which provides the output (FA) for the circuitry of FIG. 2A. The frequency divider 210 divides the output of VCO 208 by a fixed number, shown here as 1000. The output of mixer 206 provides a signal (F3) through band pass filter (B.P.F.) 212 having a frequency equal to the difference in the signals F1 and F2 to an input of additional mixer 214.
The output of the fixed R synthesizer 202 is provided through a frequency divider 216 to provide a signal (F4) to a second input of mixer 214. Frequency divider 216 divides the output of fixed R synthesizer 216 by a fixed number, shown here as 5. The output of mixer 214 provides a signal (F5) through band pass filter 218 having a frequency equal to the difference in the signals F3 and F4 to an input of a phase detector 220.
The output of the fixed R synthesizer 203 is provided through a frequency divider 222 to provide a signal (F6) to a second input of phase detector 220. Frequency divider 222 divides the output of fixed R synthesizer by a fixed number, shown here as 100. The output of the phase detector 220 is then coupled through an integrator 224 to the voltage control input of VCO 208.
Because the output frequency of VCO 208 is divided down through two mixers 206 and 214 before being provided to phase detector 220, a significant variation in the initial frequency of VCO 208 from a predicted value used to set the output frequencies of fixed R synthesizers 201-203 may prevent the circuitry of FIG. 2A from locking the output frequency of VCO 208. To presteer the output frequency of VCO 208 to a desired initial frequency, and assure lock, a user controlled D/A converter 226 is provided. The D/A converter 226 has its output connected through summer 228 along with the output of integrator 224 to provide the voltage control input to VCO 208.
In operation, the output frequency of each of the fixed R synthesizers 201-203 can be determined utilizing the equations provided with respect to FIG. 1 as follows:
F2=FRN1/R1
F4=FRN2/(5R2)
xe2x80x83F6=FRN3/(100R3)
Using the equations for F2 and F4, the frequencies of signals output from mixers 206 and 214 can be determined as follows:
F3=F2xe2x88x92F1=FRN1/R1xe2x88x92F1
F5=F3xe2x88x92F4=FR(N1/R1xe2x88x92N2/(5R2))xe2x88x92F1
With the phase detector 220 assuring that the signals F5 and F6 are equal, the frequency of signal F1 can be derived from the above equations for F5 and F6 as follows:                     F1        =                                            F              R                        ⁡                          (                                                N1                  /                  R1                                -                                  N2                  ⁡                                      (                                          5                      ⁢                      R2                                        )                                                              )                                -                                    F              R                        ⁢                          N3              /                              (                                  100                  ⁢                  R3                                )                                                                            =                              F            R                    ⁡                      (                                          N1                /                R1                            -                              N2                ⁡                                  (                                      5                    ⁢                    R2                                    )                                            -                              N3                /                                  (                                      100                    ⁢                    R3                                    )                                                      )                              
Assuming that the values for R1, R2 and R3 are respectively 5, 50 and 100, and utilizing the fact that FA=F1/10000, the frequency FA can be derived as follows:
FA=200N1xe2x88x924N2xe2x88x92N3/10.
With values for R1, R2, R3, and FR chosen as shown in FIG. 2A, values for N1, N2 and N3 are shown in FIG. 2A selected to provide an output signal FA ranging from 100-200 KHz. For the values for N1, N2 and N3 shown, frequencies at the outputs of the oscillators and inputs to phase detectors are also shown.
With the value for N1 being variable while N2 and N3 remain fixed, as shown in FIG. 2A, output resolution for the circuit of FIG. 2A, taking into account frequency divider 210, is calculated as RES=FR/(10000R1)=200 Hz. Alternatively, with N2 being variable, while N1 and N3 remain fixed, taking into account frequency divider 216, output resolution will be RES=FR/(50000R2)=4 Hz. To provide an even greater resolution N3 can be varied while N1 and N2 remain fixed, making the output resolution RES=FR/(100000R3)=0.1 Hz. Thus, by properly controlling N1, N2 and N3, the fine resolution synthesizer circuit of FIG. 2A can provide a 100-200 KHz output with as high as a 0.1 Hz resolution. Further, with the frequency output of the N3 frequency divider being 100 KHz=Fp, and N3 being altered to control FA, tsettle=4.5/(2xcfx80(Fp/10))=72 xcexcsec.
FIG. 2B shows a coarse resolution portion of the divide sum synthesizer which includes a fixed R synthesizer 204. The fixed R synthesizer 204, similar to synthesizers 201-203 of FIG. 2A, utilizes the common reference oscillator 205 to enable synchronization with a standard external source.
The output of the fixed. R synthesizer 204 (F8) is provided to the first input of a mixer 230, while a second input of mixer 230 is provided from an output (F7) of a VCO 232. The output of VCO 232 further provides the output of the circuit of FIG. 2B. The output of mixer 230 provides a signal (F9) through band pass filter 234 having a frequency equal to the difference in the signals F7 and F8 to an input of a phase detector 236.
A phase detector 238 receives a first input from the output FA of frequency divider 210 of FIG. 2B. A second input (F11) of the phase detector 238 is provided from a mixer 240 through bandpass filter 242. A first input of mixer 240 is provided from the reference oscillator 205. A second input (F10) of mixer 240 is provided as the output from VCO 244 which has its input coupled to the output of phase detector 238. The signal F10 from the output of oscillator 244 is further provided as a second input to phase detector 236. The output of phase detector 236 is then provided through integrator 246 to the voltage control input of oscillator 232.
As with oscillator 208 in FIG. 2A, oscillator 232 receives presteering from a user controlled D/A converter 248. Presteering assures that the output frequency of oscillator 232 can be locked using the circuitry of FIGS. 2A and 2B. To provide the presteering, the D/A converter 248 output is connected along with the output of integrator 246 to a summer 250. The output of summer 250, then provides the voltage control input to VCO 208.
In operation, the output frequency of the fixed R synthesizer 204 can be determined by the following equation:
F8=FRN4/R4
Further, using the equation for F8, the output frequency of the signal from mixer 230 can be determined as follows:
F9=F8xe2x88x92F7=FRN4/R4xe2x88x92F7
Further, with the mixer 240 assuring F11=F10xe2x88x92FR and phase detector 238 assuring FA=F11, F10 can be derived as follows:
F10=FA+FR
With phase detector 236 assuring F9=F10, from the equations for F9 and F10 above, we can derive F7 as follows:                     F7        =                                            F              R                        ⁢                          N4              /              R4                                -                      F            A                    -                      F            R                                                  =                                            F              R                        ⁡                          (                                                N4                  /                  R4                                -                1                            )                                -                      F            A                              
Substituting the equation for FA derived with respect to FIG. 2A, F7 is further defined as follows:
F7=FR(N4/R4xe2x88x92N1/(1000R1)xe2x88x92N2/(50000R2)xe2x88x92N3/((10000000R3)xe2x88x921)
Note from this equation for F7 it can be seen how the term xe2x80x9cdivide sumxe2x80x9d used to describe the synthesizers of FIGS. 2A-2B is derived as the xe2x80x9csumxe2x80x9d of the xe2x80x9cdividedxe2x80x9d N/R ratios.
Assuming the value for R4 is 100 and the values for components of FIG. 2A are chosen as shown, F7 is further defined as follows:
F7=100,000N4xe2x88x92200N1+4N2+N3/10xe2x88x9210 MHz
With a values for R4 and components in FIG. 2A chosen as shown, values for N4 are shown selected to provide an output signal F7 ranging from 600-1200 MHz.
With the value for N4 being variable while N1-N3 remain fixed, output resolution for the signal F7 can be calculated as RES=FR/R4=100 KHz. Alternatively, with N4 remaining fixed, while N1, N2 or N3 are varied, output resolution will remain as described with respect to FIG. 2A. For instance, with N3 being variable while N1 and N2 remain fixed, output resolution RES=FR/(1000000R3)=0.1 Hz.
Thus, by properly controlling N1-N4, the output F7 can range from 600-1200 MHz with a 0.1 Hz resolution. Further, with the frequency output of the N3 frequency divider being 100 KHz and N3 being altered to control F7, settling time, tsettle=4.5/(2xcfx80(Fp/10))=72 xcexcsec.
The present invention enables significantly less components to be utilized than in a ratio sum topology synthesizer to provide a synthesizer with a 600-1200 MHz range while maintaining a 0.1 Hz resolution and a settling time below 72 xcexcsec.
The present invention further does not require use of a fixed frequency reference oscillator as do synthesizers discussed above.
The present invention includes a xe2x80x9cvariable Rxe2x80x9d synthesizer, as opposed to a xe2x80x9cfixed Rxe2x80x9d synthesizer discussed above. The variable R synthesizer includes components similar to FIG. 1, but with the fixed R frequency divider replaced by a variable R frequency divider to enable increased control of output resolution.
In one embodiment of the present invention, the value for N may also be varied along with R to provide greater resolution. The values for N and R may be changed either incrementally in steps of one, or non-incrementally using an iterative process.
With the value for R varied to provide a desired output resolution, error will occur from the desired resolution. To reduce error in resolution, an embodiment of the present invention provides for varying the frequency of a reference oscillator, such as oscillator 100 of FIG. 1.
To provide even greater resolution, a further embodiment of the present invention utilizes multiple variable R synthesizers connected with the VCO output of one of the variable R synthesizers forming the input of a divide by R frequency divider in a subsequent variable R synthesizer.
In an additional embodiment of the present invention, multiple variable R synthesizers may be used to a provide xe2x80x9cratio sumxe2x80x9d synthesizer, the ratio sum synthesizer having an output frequency proportional to a sum of N/R ratios of their variable R synthesizers.
In one embodiment of a ratio sum synthesizer, outputs of VCOs from two variable R synthesizers are provided to inputs of a mixer. The output of the mixer is then provided as an input to one of the divide by N frequency dividers, one mixer input then providing the output of the ratio sum synthesizer.
In another embodiment of a ratio sum synthesizer, an output of a first variable R synthesizer is provided with an output of an output signal VCO to inputs of a first mixer, the output of the first mixer is then provided with the output of a second variable R synthesizer to inputs of a second mixer, the output of the second mixer is then provided with the output of a third variable R synthesizer to inputs of a phase detector, and the output of the phase detector is used to control the output signal VCO.